Red Pitaya - using STEMlab as SDR platform
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Alongside other instruments, the Red Pitaya board can be used as a SDR platform. A simple installation of the SDR Transceiver application will transform your RedPitaya board into a SDR platform.
To run the SDR on the RedPitaya board you will need to install on your computer one of the following types of SDR software such as HDSDR, SDR#, PowerSDR mRX PS, GNU Radio or similar.
Introduction[edit | edit source]
Listening to the radio with ADC and FPGA had been on my to-do list for quite some time before I discovered Red Pitaya. At that time, it was the first board that provided the exact combination of features that I was looking for, and more. I was very surprised to find out that there was no open-source Software Defined Radio (SDR) project based on Red Pitaya. So, I decided to create such a project. This was in December 2014.
The initial objectives of my SDR project could be summarised in the following points:
• get familiar with new Xilinx chips and tools,
• keep the number of lines of code low,
• make use of the existing libraries and programs.
After less than one year, in September 2015, I released the first version of the dual channel SDR transceiver that can now be used with several SDR programs and frameworks: HDSDR, Gqrx, GNU Radio, GNU Radio Companion and Pothos. Shortly after, there also appeared a version compatible with the software developed by the HPSDR project and other SDR programs supporting the HPSDR/Metis communication protocol: PowerSDR mRX PS, Quisk, ghpsdr3-alex, openHPSDR Android Application, Ham VNA, etc. Both versions of the SDR transceiver applications are available from the Red Pitaya application marketplace.
What is inside the Red Pitaya SDR transceiver applications?[edit | edit source]
When started, the SDR transceiver applications configure the FPGA and start TCP or UDP servers that communicate with SDR programs running on a remote PC.
The main blocks of the FPGA configurations are interfaces with ADC and DAC, digital down- and up-converters, FIFO buffers, configuration and status registers.
The digital down- and up-converters consist of the following blocks:
• direct digital synthesizer (DDS) generating a complex sinusoid,
• complex multiplier,
• CIC filter that is used to decrease the sample rate by a configurable factor,
• FIR filter that compensates for the drop in the CIC frequency response and reduces the sample rate by a factor of two.
Only a few custom IP cores had to be written for the FPGA configuration, thanks to the rich library of IP cores coming with Xilinx Vivado Design Suite.
The job of the TCP and UDP servers running on the on-board CPU is to transmit/receive data to/from SDR programs running on a remote PC. The servers communicate with the FPGA configuration via FIFO buffers, configuration and status registers.
The SDR programs provide graphical user interface, spectrum display, modulation/demodulation and any other functionality useful for radio applications.
For those interested in reading more about Digital Signal Processing (DSP) and Software Defined Radio (SDR), I can recommend the following on-line resources:
• The Scientist and Engineer’s Guide to Digital Signal Processing by Steven W. Smith
• dspGuru: Digital Signal Processing Articles
• ARRL: Software Defined Radio
• GNU Radio: Suggested Reading
Red Pitaya is a very interesting platform for experimenting with FPGA and DSP algorithms and sharing knowledge and experiences. It is also a nice SDR building block, thanks to the excellent open-source SDR tools.
The source code and more information about the projects based on Red Pitaya can be found here.
Dedicated platform for SDR[edit | edit source]
Red Pitaya has recently introduced even a new STEMlab product tailored for HF+50MHz SDR & RF applications that requires DAQ systems with higher precision. Improvements were done based on feedback that was received from HAMradio operators & research laboratories have many time modified part of STEMlab front-end so that they were able to connect power amplification units, pre-amplifiers & attenuators, filters, other HAMradio or scientific electronics.
STEMlab 122.88-16 SDR comes with two 16 bit ADCs, 50 ohm inputs & 14 bit DACs 50ohm outputs , three times bigger dual core ARM Cortex A9 + Xilinx Zynq 7020 FPGA, ultra low phase noise 122.88MHz clock and 1Gbit ethernet connectivity. RF inputs are improved in terms of distortions, noise & crosstalk which will significantly improve receive and use of antenna diversity. Bigger FPGA provides more real-time processing capabilities. Clock was changed from 125MHz to 122.88MHz so that it makes new STEMlab more hardware compatible with HPSDR. Good news for current STEMlab users is also that new device has not changed the form factor so it directly replaces current STEMlab platform. STEMlab will come at higher price compared to STEMlab 125-14 version, but price/performance ratio will still be very competitive in comparison with other similar devices on the market. With this improved performances & affordability we believe STEMlab 122.88-16 SDR will enable Red Pitaya community to build SDR transceivers & other scientific devices that will be able to compete with really high-end products on market available today.
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Examples of ready to use applications
- Applications for Red Pitaya STEMlab 125-14:
- SDR receiver
- SDR transceiver
- SDR transceiver compatible with HPSDR
- SDR receiver compatible with HPSDR
- Embedded SDR transceiver
- Wideband SDR transceiver
- Multiband WSPR transceiver
- Multiband FT8 transceiver
- Pulsed NMR system
- Multichannel Pulse Height Analyzer
- Scanning system
- Vector Network Analyzer
- Applications for Red Pitaya STEMlab 122.88-16 SDR:
- SDR transceiver
- SDR transceiver compatible with HPSDR
- SDR receiver compatible with HPSDR
- Embedded SDR transceiver
- Multiband WSPR transceiver
- Multiband FT8 transceiver
- Pulsed NMR system
- Vector Network Analyzer